Integrated Memory and Logic
Team: Jeffrey Bokor, Tsu-Jae King Liu, Ramamoorthy Ramesh, Sayeef Salahuddin
Large data sets coupled with long network latency result in significant energy inefficiencies in data centers. Processors consume energy mostly in the idle state, waiting for the network to return a data query or maintaining availability to service a remote query into local memory. Due to long latency, network fabrics also have low utilization, consuming much more power than that needed to move data around. Disaggregation of processing and memory resources and optimization of the network fabric, enabled by new memory technologies and silicon photonics, can provide for dramatically improved energy efficiency of warehouse-scale computers (WSCs).
In the BETR Center we are pursuing the goal of high-density non-volatile memory that can be monolithically integrated with CMOS circuitry, such as nanometer-scale magnetic and ferroelectric devices, and nano‐electro‐mechanical switches (NEMS) which can be implemented in an air‐gapped interconnect back‐end‐of‐line process. This research involves fundamental scientific studies, to elucidate physical phenomena such as electric-field control of magnetization in multiferroic-ferromagnet heterostructures (for voltage-controlled operation of nanomagnetic memory devices), as well as the development of integrated memory+logic fabrication processes and metrology for characterization of three-dimensionally integrated circuit structures.