Wafer-scale silicon photonics/CMOS 3D-integration (Stojanović group)
A. Optically Sampled Analog-to-Digital-Converter (O-ADC)
As the silicon-photonics (SiPh) processes mature, high-performance optical blocks integrated close to CMOS can be leveraged to alleviate system-level performance bottlenecks. For example, the accuracy of conventional analog-to-digital-converters (ADCs) for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, the Stojanović group developed an ADC that uses low-jitter (<26 fsrms) optical pulses to sample the input signal.4 The team then realized a prototype two-channel ADC in a 3D integrated platform with 65nm CMOS and silicon-photonics connected using high-density through-oxide-vias (TOVs), representing the first SiPh O-ADC fully integrated on a single-chip. Figure 1 shows the architecture of an O-ADC. An MLL-based external optical pulse source generates pulses at wavelengths λ1 to λN with a given pulse width, spacing, and repetition rate. An electro-optic modulator modulates the intensity of these pulses with the input signal. These pulses are then coupled into a SiPh chip where they are separated by the tunable double-ring bandpass filters matched to λ1–λN. Thermal tuning circuits on the CMOS chip tune the filters to the desired wavelength. Photodetectors in each channel convert the optical pulses into current pulses that are amplified and digitized by the analog frontend (AFE) on the CMOS chip. The O-ADC presented here is fabricated in a 300mm CMOS foundry and achieves >5.5-bit resolution and input sampling bandwidth of 45 GHz.
Figure 1. Architecture of an optically sampled analog-to-digital-converter (O-ADC).
B. Relay-Based Digital Integrated Circuits
In a collaborative project between the Liu and the Stojanović groups, reliable operation of relay-based digital integrated circuits (ICs) with 50 mV supply voltage was demonstrated.2, 5 No other digital IC device technology developed to date has even been projected to be able to operate at such low voltages at room temperature. Because a relay is much more functional than a transistor, various two-input logic functions (including NOT, AND, OR, and XOR) can be implemented with only two relays using pass-gate circuit topology, which minimizes the number of relays and the delay per digital function. Figure 2 shows a 2:1 multiplexer (MUX) implemented with only two relays; for comparison, a CMOS implementation requires at least four transistors.
Figure 2. Demonstration of ultra-low-voltage operation of a 2-to-1 multiplexer integrated circuit: (a) schematic circuit diagram and (b) truth table; measured voltage waveforms (c) at 300 K (VBP=15.5 V, VBN=-14.6 V) and (d) at 77 K (VBP=17.07 V, VBN=-14.71 V).
C. Single-Chip Optical Phased Array (OPA)
The Stojanović group developed an optical phased array (OPA) design based on a wafer-scale 3-D photonics/CMOS integration platform to resolve I/O and electronics density problems.6 This research directly addresses the need for integrated OPAs to support 500-1000 elements in spite of stringent area/power/cost constraints in order to be a reliable solid-state alternative to mechanical beam scanners for automotive LiDAR. The team designed a compact single-chip OPA through wafer-scale 3-D integration of silicon photonics and CMOS, as shown in Figure 3. Flexible and ultra-dense connections with through-oxide vias (TOVs) resolve the I/O density issue. Moreover, low-voltage L-shaped phase shifters and compact, efficient switch-mode drivers, connected vertically using TOVs, remove wiring and placement overhead and achieve a large active array aperture within a compact die. This OPA prototype achieves wide-range 2-D steering while consuming 20 mW/element average power. Furthermore, 3-D integration allows the photonics to be highly customized independent of electronics, opening up unlimited opportunities for integrated free-space system design.
Figure 3. Overview of the 3-D heterogeneous integration platform used to construct the single-chip OPA.
- K. Settaluri, C. Lalau-Keraly, E. Yablonovitch, and V. Stojanović, “First Principles Optimization of Opto-Electronic Communication Links,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 5, pp. 1270-1283, May 2017.
- Z. A. Ye, S. Almeida, M. Rusch, A. Perlas, W. Zhang, U. Sikder, J. Jeon, V. Stojanović and T.-J. K. Liu, “Demonstration of Sub-50 mV Digital Integrated Circuits with Microelectromechnical Relays,” IEEE International Electron Devices Meeting, San Francisco, CA, Dec 2018.
- A.H. Atabaki et al., “Integrating Photonics with Silicon Nanoelectronics for the Next Generation of Systems on a Chip,” Nature, vol. 556, pp. 349-354, Apr. 2018.
- N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, N. Fahrenkopf, S. Kruger, T. Ngai, Y. Timalsina, M. Watts, and V. Stojanović, “An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS,” 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, pp. 1-2, Dec 2020.
- X. Hu, S.F. Almeida, Z.A. Ye, and T.-J. King Liu, “Ultra-Low-Voltage Operation of MEM Relays for Cryogenic Logic Applications,” 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 34.2.1-34.2.4, Dec 2019.
- T. Kim, P. Bhargava, C.V. Poulton, J. Notaros, A. Yaacobi, E. Timurdogan, C. Baiocco, N. Fahrenkopf, S. Kruger, T. Ngai, Y. Timalsina, M.R. Watts, and V. Stojanović, “A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform,” IEEE Journal of Solid-State Circuits, vol. 54, pp. 3061-3074, Nov. 2019.